1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, particularly to a semiconductor device comprising an insulated-gate field effect transistor having a contact hole formed in an inter-layer insulating film on a source/drain region (hereinafter referred to as S/D region) adjacent to a gate electrode.
2. Description of the Prior Art
A higher integration level has been requested for a semiconductor memory in recent years, therefore, it is necessary to further fine a pattern. As one of the means for realizing a higher integration level, insulated-gate field effect transistor is further fined which serves as a component of the semiconductor memory.
FIG. 1A to FIG. 1F are sectional views for explaining a method for manufacturing an insulated-gate field effect transistor having a contact hole formed in an inter-layer insulating film on an S/D region of both sides of a gate electrode. The insulated-gate field effect transistor uses an insulated-gate field effect transistor having a floating gate in an EPROM cell.
FIG. 1A shows a state after a floating gate and a control gate are formed and moreover a S/D region is formed in a surface layer of a semiconductor substrate of both sides of the control gate.
In FIG. 1A, symbol 1 is a semiconductor substrate, 2 is a gate insulating film on the semiconductor substrate 1, 3a is a floating gate on the gate insulating film 2, 3c is a control gate formed above the floating gate 3a through an insulating film 3b, 4 is an insulating film on the control gate 3c, and 5a and 5b are S/D regions formed in the surface layer of the semiconductor substrate 1 of both sides of the control gate 3c.
Under the above state, as shown in FIG. 1B, an insulating film 6 is formed by covering the gate insulating film 2, floating gate 3a, insulating film 3b, and control gate 3c in order to form a side wall.
Then, as shown in FIG. 1C, an insulating side wall 6a is formed on the side surface of the gate electrode 3 by anisotropically etching the insulating film 6.
Then, as shown in FIG. 1D, an inter-layer insulating film 7 is formed on the entire surface.
Then, as shown in FIG. 1E, the inter-layer insulating film 7 on the S/D region 5a is selectively etched and removed to form a contact hole 7a in the inter-layer insulating film 7 on the S/D region 5a.
Then, as shown in FIG. 1F, a conducting film is formed and thereafter patterned to form a source/drain electrode (hereinafter referred to as S/D electrode) or interconnection layer 8 which connects with the S/D region 5a through the contact hole 7a.
For the above existing method for fabricating a semiconductor device, however, it is necessary to decrease the size of the S/D regions 5a and 5b and bring the contact hole 7a as closely to the gate electrode 3 as possible in order to integrate elements at a high density. For this reason, in the case that a deviation of an alignment occurs when patterning a contact hole, the contact hole 7a may be formed by etching the side wall 6a as shown in FIG. 2.
Therefore, when an S/D electrode or interconnection layer is formed in the contact hole 7a, the thickness of an insulating film between the gate electrode 3 and the S/D electrode or interconnection layer fluctuates. For this reason, a problem occurs that parasitic capacitance fluctuates or accumulated electric charges fluctuate due to leakage of them.
Besides, an existing example is shown in a patent document of the Japanese unexamined publication (KOKAI) 3-96271. In this case, the same problem as described above might occur, too.